CENTRALE LYON - Post Doctoral Open and Flexible System-Level Evaluation Framework for Emerging AI Computing Architectures

Emerging computing technologies – non-volatile and ferroelectric memories, analog and digital in-memory computing, silicon photonics, 3D integration, and heterogeneous chiplets – offer major gains in energy efficiency, latency, bandwidth, and functionality. Their potential cannot, however, be established from device or circuit results alone: it requires a rigorous link between technology characteristics, architectural choices, workload mapping, and application-level figures of merit.

The Electronics group at the Lyon Institute of Nanotechnology (INL) is seeking a (m/f) postdoctoral researcher to develop an open, modular and extensible system-level evaluation framework for design space exploration (DSE) and system-design-technology co-optimization (SDTCO) of emerging computing architectures. The focus is at the interface of computer architecture, accelerator design, performance modelling and hardware-software codesign, while making systematic use of lower-level device, circuit and array results so that architectural conclusions remain physically credible.

The objective is to convert low-level results – compact models, measured or simulated KPIs, variability and reliability constraints, and multi-objective Pareto fronts – into parameterized architectural models supporting efficient exploration of accelerators for emerging AI workloads. The framework must enable both bottom-up projection, from device/circuit/array choices toward system performance, and top-down constraint propagation, from targets for energy, latency, throughput, accuracy, robustness and area toward technology and circuit requirements. It will consolidate ongoing INL activities in predictive system assessment, DTCO, emerging memories, compute-in-memory and photonic computing, integrating or extending existing components with emphasis on openness, reproducibility and reusability.

A core scientific challenge is to represent cross-layer trade-offs without hiding their origin: rather than isolated energy or latency numbers, the framework should expose bottlenecks, sensitivities, feasibility limits, break-even points and opportunities and identify the regimes in which a technology becomes advantageous. Target workloads span edge inference through to transformer-inspired models, with use cases in vision, audio and sensor processing, sparse and vector/matrix operations, and on-device learning.

Expected outcomes: a maintainable evaluation environment combining fast exploration with selected higherfidelity validation paths; cross-layer models and interface contracts, reusable data schemes, benchmarking flows, system-level Pareto analyses and design guidelines for emerging AI accelerators – a decision-support instrument for future research projects.

Candidate profile: PhD in Electrical or Electronic Engineering, Computer Engineering, Computer Science or a related discipline, with a strong background in several of: computer architecture and AI accelerators; performance, energy and area modelling; design space exploration and multi-objective optimization; hardwaresoftware co-design and workload mapping; emerging memories, compute-in-memory or photonic computing. Strong Python skills and sound software-engineering practice are essential; experience with SystemC, C/C++, RISCV simulation, QEMU, PyTorch/ONNX workload flows, architecture simulators (NeuroSim, CiMLoop/AccelForge, Timeloop or similar) will be appreciated. Familiarity with circuit-level modelling or EDA is an asset, but the focus is architectural and system-level research.

Environment: the position is hosted by the Electronics group at INL (UMR CNRS 5270), Ecole Centrale de Lyon, Écully, France – an interdisciplinary environment spanning devices, circuits, architectures, design automation, photonics and integrated systems, with national and European collaborations.

Starting date: Fall 2026

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