Senior Verification Engineer

Salary: £75,000 - 85,000 per year

Requirements:

• Degree in Electronic Engineering, Computer Engineering, or a related discipline.
• At least 3 years experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM experience.
• Good understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency with Python, Tcl or Bash scripting skills.
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification while maintaining quality.
• Ability to collaborate effectively across multiple engineering teams.
• Desirable experience in 4G/5G, NTN, satellite communications or DSP systems.
• Desirable experience with modem architectures and Layer 1 processing.
• Desirable experience with Formal Verification, FPGA prototyping and CI environments.
• Desirable experience with MATLAB or equivalent modelling tools.

Responsibilities:

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Carry out directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration.
• Contribute to automation, regression testing and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior engineers.

Technologies:

• AI
• Bash
• FPGA
• Hardware
• Support
• Linux
• Matlab
• Python
• SystemVerilog

More:

We are a specialist RTL team developing advanced communications technology across ASIC and FPGA platforms. This is an opportunity to work on technically challenging projects covering IP development, integration, and verification, while supporting and mentoring more junior engineers.

last updated 38 week of 2026