Senior Verification Engineer

Salary: £65,000 - 80,000 per year

Requirements:

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• Proven experience verifying ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Good understanding of RTL design and digital hardware development.
• Experience with coverage-driven and assertion-based verification techniques.
• Linux proficiency and scripting skills (Python, Tcl, Bash or similar).
• Strong debugging, analytical and communication skills.
• Desirable experience in communications, networking, aerospace, defence or other high-performance digital systems.
• Desirable experience with digital signal processing (DSP) or complex hardware architectures.
• Desirable experience with Formal Verification or FPGA prototyping.
• Desirable experience with CI/CD, automated regression environments or MATLAB/Simulink.

Responsibilities:

• Plan, develop and execute verification activities for complex digital designs and subsystems.
• Develop and execute verification strategies for complex ASIC and FPGA designs.
• Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models.
• Debug RTL and verification issues, ensuring designs meet quality and performance requirements.
• Collaborate with design, FPGA and systems teams throughout the development lifecycle.
• Support automation, regression testing and continuous improvement initiatives.
• Mentor junior engineers and contribute to technical reviews.

Technologies:

• Bash
• CI/CD
• FPGA
• Hardware
• Support
• Linux
• Matlab
• Python
• SystemVerilog

More:

We are an innovative technology company developing advanced digital hardware and signal processing solutions. We are seeking a Senior Verification Engineer to join our growing engineering team in Bristol or Cambridge on a permanent or contract basis. This is an excellent opportunity to work on technically challenging projects alongside experienced hardware, FPGA and verification engineers in a collaborative ASIC and FPGA development environment, helping to ensure robust verification methodologies, high-quality deliverables and successful project outcomes.

last updated 39 week of 2026